1. Field of the Invention
The present invention relates to the field of information processors. More specifically, the present invention relates to devices and procedures for accessing a register buffer that maintains memory management information within a processor.
2. Prior Art
Modern computer systems utilize different techniques for addressing memory. Memory may be used for storing information or for storing program instructions for the computer systems. Often, the memory storage space is divided into segments and utilized by the computer system by indicating a particular segment. When a computer program changes a value stored in memory, it is perforating a "store" operation. And when the computer is retrieving an instruction or data from memory, it is performing a "load" operation. Each of these load and store operations require an address that specifies a location in memory. In a store operation, the address specifies a location in memory that is available for storing the data. In a load operation, the address specifies the location in memory where the desired instruction or data resides.
Typically, in a modem computer system, there are several different varieties of addressing reflecting different levels of abstraction and different protection levels. For example, in the Intel architecture processor, there are the logical, linear, and physical addresses. Further, memory may be divided into different segments with each segment managed differently. Segment information is stored in a special buffer or register file. Reference is made to the i486 Microprocessor Programmer's Reference Manual, from Intel Corporation, Osborne McGraw-Hill, 1990. Chapters 4-6 describe memory management and memory protection levels and the use of selector and descriptor information related to the segment register file.
The logical address is specified in the assembly language or machine code program, and consists of a selector and an offset. The offset is formed by adding together three components: base, scaled index and displacement. The logical address space is, therefore, segmented. The logical address (consisted of segment, offset) is transformed to a flat linear address by adding a segment base corresponding to the segment selector to obtain a linear address. Both the logical and linear address spaces may be larger than the amount of physical memory in a system. A technique called virtual memory is used to translate the linear address into a physical address used to address a limited amount of physical memory. The limited amount of physical memory is extended by secondary storage, such as a hard disk drive.
Addressing modes am motivated by several reasons. First sometimes addressing modes permit programs to be smaller (e.g., by reducing address size). Instead of placing a 32-bit logical offset constant in an instruction, they sometimes permit a smaller 1 byte specification of a register, for example. (Note that this is not always true) Second, addressing modes permit programs and subroutines to be written when the addresses of data are not known in advance. The address can be calculated from input and placed in a register. Third, addressing modes permit some frequent calculations to be encoded within the memory reference instruction, rather than requiring separate instructions.
As discussed, memory can be divided into one or more variable length segments, which can be swapped to disk or shared between programs. Memory can also be organized into one or more "pages". Segmentation and paging are complementary. Segmentation is useful to application programmers for organizing memory in logical modules, whereas pages are useful to the system programmer for managing the physical memory of a system. Typically, a segmentation unit is used to translate the logical address space into a 32-bit linear address space. A paging unit is then used to translate this linear address space into a physical address space. It is this physical address that appears on a processor's address pins.
The AGU of a processor manipulates a segment register file (SRF) which contains information related to segments used to access memory within a computer system. This information includes memory management and protection information. As discussed above, for information related to memory protection (limit checking, privilege levels, selector and descriptor table usage) reference is made to chapter 5 of the i486 Microprocessor Programmer's Reference Manual, from Intel Corporation, Osborne McGraw-Hill, 1990. Since many instructions involve a memory access of some type, the SRF is utilized many times by a typical processor. It would be advantageous to provide a mechanism allowing liberal access to the SRF without causing resource conflicts between pipelined instructions. Generally, it would be advantageous to provide an efficient mechanism for allowing an AGU to update a segment register file within a pipeline processor while simultaneously permitting reads of other segment registers. The present invention offers such new and advantageous functionality.
Accordingly, it is an object of the present invention to provide an efficient AGU within a processor. It is also an object of the present invention to provide a mechanism and procedure for efficiently reading and writing to a segment register file within a pipeline processor. It is another object of the present invention to provide an efficient pipeline format for use in reading and writing information to a segment register file within an AGU in order to reduce resource conflicts between pipelined instructions that need to read and write to the segment register file. It is also an object of the present invention to provide the above within a pipeline that allows segment register reads and writes to occur in different pipestages of the corresponding instructions. It is yet another object of the present invention to provide such efficient functionality within a processor that is superscalar. These and other objects of the present invention not specifically mentioned above will become clear upon discussions of the present invention hereinafter.